As a Design Verification Engineer, you will be responsible for developing verification plans and architecting test benches to validate DUT (Devise Under Test) functionality in simulation of application specific integrated circuit (ASIC/Integrated Circuit).
In this role you will:
* Interpreting architectural and design requirements * Writing verification test plans and requirements * Developing and using complex test benches * Implementing directed and constrained random test cases * Collecting, analyzing, and enhancing functional and code coverage * Debugging issues in the requirements, tools, simulation environment, test cases, and DUT * Performing Object Oriented programming (System Verilog and C++) * Participating in System Verilog Verification using a framework such as UVM or other industry standard methodologies
* Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. OR Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience. * Proficient with SystemVerilog, HDL languages, Object Oriented Programming and Scripting Languages. * Pre- and post- silicon debug (HW lab debug and Simulation); and, Skills to use Logic analyzers and Oscilloscopes * Verification automation and scripting. * Use Perl/Shell/Python scripting skills and Extensive markup language XML to design/simulation environment automation. * Hardware/Firmware interaction and Firmware programming; and, knowledge of Microprocessors and assembly
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
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