Facebook AR/VR focuses on delivering Facebook's vision through Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Facebook Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR & VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.
Facebook is looking for a Silicon Audio Architect who will work with a world-class group of researchers and engineers. This ideal candidate will understand the full stack from Audio speaker/mic interfacing to algorithms and architecture down to silicon back end and qualification to ensure consistency from Architecture to Product. We are seeking a Silicon Audio Architect to drive a silicon design that includes functions such as render, spatialization, beam forming, noise cancellation and other compute.
* Architect designs to surpass state of the art for metrics such as compute, bandwidth and power consumption.
Work across disciplines, brainstorm big ideas, work in new technology areas, juggle/coordinate multiple initiatives, drive a concept into a prototype and ultimately guide the transition into a high-volume consumer product.
Make tradeoffs between general purpose and custom compute mechanisms.
Model data-flows, create detailed cost/benefit analysis and estimate power consumption.
Perform architectural studies including selecting ASIC technologies, FPGA ASIC emulation, and other system topics such as interface approaches, etc.
Support FPGA/RTL engineers implementing such algorithms for real time evaluation or silicon integration and Silicon SoC Architects with integration, documentation and implementation.
Produce detailed documents and SystemC models matching the proposed ASIC implementation, and produce detailed tradeoff analyses for executive review and product roadmap decisions.
Travel both domestically and internationally.
* 7+ years of experience as a Digital Design Engineer, Silicon µArchitect, and Silicon Architect for production silicon.
1+ years of experience with methods for partitioning a solution across hardware and software, digital, and other multi-disciplinary boundaries in a system solution.
1+ years of experience evaluating architectural tradeoffs such as speed, performance, power, area.
1+ years of experience employing scientific methods to debug, diagnose and drive the resolution of cross-disciplinary system issues.
BS EE/CS or equivalent experience.
* Top down knowledge in high-level-model to HW mapping.
Knowledge of industry trends and disruptive technologies.
Experience programming in C or C++.
DSP coding and optimization experience.
Experience working effectively as an individual and in a multidisciplinary international team.
Ability to collaborate and/or lead in a team environment.
Capable of dealing with ambiguity with a fast changing consumer electronics field.
Results oriented, self-motivated, proactive with demonstrated creative & critical thinking.
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