Senior Design Verification Engineer Silicon Labs
Austin, TX

Job Description

We are Silicon Labs. We are the leading provider of silicon, software and solutions for a smarter, more connected world

We hire the most innovative talent in the world to solve the industry's toughest problems, providing our customers with significant advantages in performance, energy savings, connectivity and design simplicity. Silicon Labs' software and mixed signal engineering teams create solutions for customers in diverse markets including the Internet of Things, (IoT), internet infrastructure, TV tuners, as well as automotive and consumer radios. Our solutions are in products from the market leaders in home automation, electric vehicles, green technology, smart TVs and home voice control automation. We take pride in our products and in our people, and that's one of the many reasons we continue to be awarded Most Respected Public Semiconductor Company by the Global Semiconductor Alliance.

How Silicon Labs Works

We are an elite team of IC Design and Verification, Validation, Software and HW/Tools engineers focused on developing and validating key components of the Silicon Labs IoT product portfolio. Our team has a deep understanding of all aspects of our MCU and Wireless products, from design to delivering a complete customer friendly system. We have a passion for what we do, take immense pride in the technology that we deliver, and always seek out better ways to serve our customers.

Why this position matters

The Internet of Things is a fast growing, innovative market. Silicon Labs has invested in a number of exciting and market-leading highly integrated mixed signal SoCs aimed at IoT. The low power and Wireless MCUs that we develop will be deployed in literally millions of products worldwide; IoT is the future of Silicon Labs and the Design Verification team is an integral part of the initiative.

Responsibilities

* Block and IP Verification
* Block level verification to validate block performance and adherence to requirements
* Generate and execute verification plan
* Architect and implement testbenches using directed, random, and assertion-based methods
* Coverage analysis
* Verification of mixed-signal IP integration, including real-number modeling
* SoC Integration and Verification
* Define, test and debug use cases for the SoC
* Verify and debug low-power design
* Flows and Methodology
* Improve flows and methodologies to streamline IP development and integration.

Requirements

* 5+ years of design experience
* Industry experience developing testbenches with SystemVerilog and UVM is required
* Knowledge of scripting/language (Python, PERL, shell, TCL)
* Design/Verification skills
* Software/Firmware coding (C)
* SystemVerilog Assertion and coverage analysis
* Low-power implementation (UPF, CPF)



Benefits & Perks

* Great medical (Choice of PPO or Consumer Driven Health Plan with HSA), dental & vision plans
* Highly competitive salary
* 401k plan with match and Roth plan option
* Equity rewards (RSUs)
* Employee Stock Purchase Plan (ESPP)
* Life/AD&D and disability coverage
* Flexible spending accounts
* Adoption assistance
* Back-Up childcare
* Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)
* Up to 25 days off per full year, (2 weeks of vacation, 1 week floating holidays, & 10 company holidays)
* 3 paid volunteer days per year
* Charitable contribution match
* Tuition reimbursement
* Free downtown parking
* Onsite gym
* Monthly wellness offerings
* Free snacks
* Monthly company updates with our CEO

We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.