At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The candidate must have demonstrated experience in several of the following areas:
* RTL Synthesis/Physical Synthesis * Design constraint creation (SDC) & debug * Static timing analysis, Power Analysis (Static, Dynamic, Leakage) * Timing optimization esp. in Physical Synthesis realm * Ability to read/understand high level RTL description * Impact of synthesis on back-end timing closure in P&R, be able to take problems from P&R and create actionable items to improve synthesis flow * Low power implementation with knowledge of UPF/CPF * Knowledge of basic DFT * CAD flow develop/debug/optimize * Knowledge of challenges with lower nodes 10nm and below * Proven expertise with hands-on work on improving full flow PPA on challenging blocks - both high freq and low power * Scripting experience - TCL, PERL
In addition following soft skills are a MUST-HAVE:
* Strong communication and interpersonal skills
* Capable of influencing outcomes among customers, R&D and Cadence technical team members.
* Can mentor junior team members regarding technical topics for a given project
* Good consulting/client skills.
* Basic project and task management skills
* Be able to build strong relationships both internal and external
* Relevant experience of 5-7 years is must have
We're doing work that matters. Help us solve what others can't.
Cadence Design Systems is an electronic design automation and intelligent system design provider delivering hardware, software, and IP for electronic design.