Design Verification Engineer Qualcomm
San Diego, CA

Job Description

Job Detail

Job Id E1971571 Job Title Design Verification Engineer Post Date 04/14/2019 Company Qualcomm Technologies, Inc.

Job Area Engineering - Verification

Location California - San Diego

Job Overview Qualcomm CDMA Technologies, a.k.a. QTI - http://www.qualcomm.com/qct/, is the world leader in wireless ICs powering the majority of 3G, 4G & 5G devices, the largest fabless semiconductor in the world, and is consistently ranked near the top of Fortune's list of "100 Best Companies to Work For". Join QCT's design verification team in verifying the high speed SerDes PHY for Qualcomm's next generation modem system chipsets. The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The responsibility of the position involves comprehensive pre-silicon, post-silicon test planning, testbench development using the advanced verification methodology such as SystemVerilog-UVM, SyatemVerilog-OVM, Analog/mixed signal simulation, Assertion development, & Formal verification (Property checking). Responsibilities: You will be responsible for understanding the analog-digital partition at system level, develop testplan for functional and circuit performance verification, testbench architecture, develop the scalable testbench using the HVLs, test case development, debugging, coverage model development, & coverage closure. You will be working with analog circuit design team, digital design team, analog modeling, characterization team, controller subsystem team, & SoC integration team to complete the successful PHY level verification, integration into subsystem & SoC, & post-silicon validation. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field.

5+ years ASIC design, verification, or related work experience. " id="hdnMinimumQualifications" />Bachelor's degree in Science, Engineering, or related field.

5+ years ASIC design, verification, or related work experience. Preferred Qualifications 4+ years of experience in digital design & verification (DV), test planning, problem solving, debug, adversarial testing, strong working knowledge of system verilog testbench, UVM methodology, Low power design concepts, Low power verification methodology, Verification of high speed parallel/serial IO interfaces such as D-PHY, M-PHY, SATA, Camera port, Display Port, PCIe Gen3/4, USB2.0, USB3.0, USB4.0 & HDMI, DDRPHY and/or DRAM controller, Well versed with JEDEC protocol for LPDDR2/3/4/5 & PCDDR2/3. Analog Mixed Signal (AMS) Verification and Functional coverage development & analysis. Education Requirements Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering or equivalent experience" id="hdnEducationalRequirements" />Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering or equivalent experience

Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering or equivalent experience Keywords Design Verification, UVM, Systemverilog, SVA, AMS Verification, Low Power Verification, Formal Verification, Testbench Architecture, Coverage, SerDes Verification