Facebook AR\VR focuses on delivering Facebook's vision through Augmented Reality (AR) and Virtual Reality (VR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Facebook Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR and VR devices where our real and virtual world mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms.
In this highly visible role, you will be part of the team effort interfacing with all disciplines, with a critical impact on getting functional products to millions of customers quickly. We are looking for Design Verification Engineer to provide technical leadership in Formal Verification techniques across the board for verification of IPs, Subsystems and large SoCs.
* Provide technical leadership in Formal Verification
Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level
Work with cross-functional teams to identify best verification methodology for all aspects of our designs
Define and close coverage targeted by specific Formal Verification Technique at IP, Subsystem and SoC level
Work with Architecture and Design team to come up with Formal driven specification and implementation
Work with Firmware and Security Architecture and Design team to close security coverage
Build environments for Formal Verification and deploying the tools
Build highly automated environments that are friendly to frequent product requirement changes
Evaluate and recommend EDA solutions for Formal Verification
Provide training for internal teams and mentoring engineers related to Formal Verification Technology
* 7+ years of experience in RTL Design and Verification area of which 4+ years of experience in Design Verification, including 3+ years of experience in Formal Verification
Knowledge of Formal Property and Formal Connectivity Verification
Knowledge of System Verilog UVM testbenches
Experience with simulators and waveform debugging tools
* Experience in formal property verification of complex compute blocks like DSP, CPU or HW accelerators
Experience with complex SoCs
Knowledge of coverage merging across simulation and formal
Moderate scripting experience
Knowledge of security concepts
Formal verification expertise in clock domain crossing, IP-XACT based register verification and low power
Experience with development of fully automated flows from specification to fully verified designs
Python scripting experience
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